已通过高速接口与数据通路v3.0.0

DDR 帧缓存与乒乓缓存助手

设计 DDR 读写缓存、VDMA/AXI DMA、地址映射、ping-pong buffer、帧边界和带宽仲裁策略。适合图像、雷达矩阵、采集回放、AI 前后处理和多路缓存项目，重点解决“DDR IP 能校准通过不代表系统能稳定跑，真实瓶颈在 burst 效率、仲裁、读写冲突和帧边界”这类真实 FPGA 项目问题。输出 DDR 缓存方案、地址映射与带宽表和可执行的后续动作。

查看 Skill 详情

Benchmark

96.9%

通过率

检查项

low

风险等级

publishable

复核结论

自动检查

SKILL.md format and section validation

通过

skills/ddr-frame-buffer-planner/SKILL.md

Required frontmatter and sections are present.

Hardcoded secret scan

通过

skills/ddr-frame-buffer-planner

No private key, cloud key, token, or long generic secret matched.

High-risk behavior scan

通过

skills/ddr-frame-buffer-planner

No recursive deletion, cloud metadata access, encoded shell, or unreviewed transfer matched.

Declared dependency inventory

通过

skills/ddr-frame-buffer-planner

No runtime dependency manifest is included in this Skill package.

Sandbox dry-run readiness

通过

skills/ddr-frame-buffer-planner

Package is documentation/reference only, so runtime sandbox is marked as dry-run ready.

Benchmark evidence completeness

通过

skills/ddr-frame-buffer-planner/SKILL.md

Score 92, level A-, pass rate 96.9%.

Human review gate

通过

skills/ddr-frame-buffer-planner/SKILL.md

Status is reviewed.

Benchmark 套件

Format and metadata fixtures12/13

content/audit/evidence/ddr-frame-buffer-planner/bm-fmt.json

IC workflow scenario cases31/32

content/audit/evidence/ddr-frame-buffer-planner/bm-scenario.json

Safety and guardrail cases12/13

content/audit/evidence/ddr-frame-buffer-planner/bm-safety.json

Regression and replay cases7/6

content/audit/evidence/ddr-frame-buffer-planner/bm-regression.json

包盘点

包哈希: sha256:28177c85dc132f62
文件数: 7
可执行文件: 0
复核结论: publishable
复核团队: IC Hub 审核团队
复核时间: 2026-06-11

已知限制与下一步

适用边界

审核结论只覆盖 Skill 包内容、安装计划和公开样例，不替代真实 FPGA 项目的上板测试、客户验收和安全审批。

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