已通过板卡调试与系统联调v3.0.0

DDR 校准与压力测试助手

分层定位 DDR 初始化、校准、读写、突发、仲裁、温漂和压力测试问题。适合Zynq、Kintex、Artix、Intel/国产 FPGA 的 DDR3/DDR4/LPDDR 项目，重点解决“DDR 问题可能来自硬件走线、电源、时钟、约束、IP 参数或用户逻辑访问节奏”这类真实 FPGA 项目问题。输出 DDR 调试分层表、压力测试计划和可执行的后续动作。

查看 Skill 详情

Benchmark

96.6%

通过率

检查项

low

风险等级

publishable

复核结论

自动检查

SKILL.md format and section validation

通过

skills/ddr-mig-calibration-debug/SKILL.md

Required frontmatter and sections are present.

Hardcoded secret scan

通过

skills/ddr-mig-calibration-debug

No private key, cloud key, token, or long generic secret matched.

High-risk behavior scan

通过

skills/ddr-mig-calibration-debug

No recursive deletion, cloud metadata access, encoded shell, or unreviewed transfer matched.

Declared dependency inventory

通过

skills/ddr-mig-calibration-debug

No runtime dependency manifest is included in this Skill package.

Sandbox dry-run readiness

通过

skills/ddr-mig-calibration-debug

Package is documentation/reference only, so runtime sandbox is marked as dry-run ready.

Benchmark evidence completeness

通过

skills/ddr-mig-calibration-debug/SKILL.md

Score 94, level A, pass rate 96.6%.

Human review gate

通过

skills/ddr-mig-calibration-debug/SKILL.md

Status is reviewed.

Benchmark 套件

Format and metadata fixtures11/12

content/audit/evidence/ddr-mig-calibration-debug/bm-fmt.json

IC workflow scenario cases29/30

content/audit/evidence/ddr-mig-calibration-debug/bm-scenario.json

Safety and guardrail cases11/12

content/audit/evidence/ddr-mig-calibration-debug/bm-safety.json

Regression and replay cases6/5

content/audit/evidence/ddr-mig-calibration-debug/bm-regression.json

包盘点

包哈希: sha256:7706fa33c4ea6334
文件数: 7
可执行文件: 0
复核结论: publishable
复核团队: IC Hub 审核团队
复核时间: 2026-06-11

已知限制与下一步

适用边界

审核结论只覆盖 Skill 包内容、安装计划和公开样例，不替代真实 FPGA 项目的上板测试、客户验收和安全审批。

Ready for controlled download once account authorization is connected.