已通过高速接口与数据通路v3.0.0

多时钟 CDC/RDC 设计助手

为多时钟 FPGA 设计梳理 clock/reset domain、CDC/RDC 边界、同步策略、约束和验证方法。适合任何包含采集时钟、处理时钟、DDR 时钟、总线时钟、显示时钟的 FPGA 项目，重点解决“很多上板偶发 bug 来自跨时钟、复位释放顺序或误用 clock enable，而仿真很难复现”这类真实 FPGA 项目问题。输出 CDC/RDC 风险矩阵、同步策略清单和可执行的后续动作。

查看 Skill 详情

Benchmark

96.4%

通过率

检查项

low

风险等级

publishable

复核结论

自动检查

SKILL.md format and section validation

通过

skills/multi-clock-cdc-reset/SKILL.md

Required frontmatter and sections are present.

Hardcoded secret scan

通过

skills/multi-clock-cdc-reset

No private key, cloud key, token, or long generic secret matched.

High-risk behavior scan

通过

skills/multi-clock-cdc-reset

No recursive deletion, cloud metadata access, encoded shell, or unreviewed transfer matched.

Declared dependency inventory

通过

skills/multi-clock-cdc-reset

No runtime dependency manifest is included in this Skill package.

Sandbox dry-run readiness

通过

skills/multi-clock-cdc-reset

Package is documentation/reference only, so runtime sandbox is marked as dry-run ready.

Benchmark evidence completeness

通过

skills/multi-clock-cdc-reset/SKILL.md

Score 94, level A, pass rate 96.4%.

Human review gate

通过

skills/multi-clock-cdc-reset/SKILL.md

Status is reviewed.

Benchmark 套件

Format and metadata fixtures11/11

content/audit/evidence/multi-clock-cdc-reset/bm-fmt.json

IC workflow scenario cases27/28

content/audit/evidence/multi-clock-cdc-reset/bm-scenario.json

Safety and guardrail cases11/11

content/audit/evidence/multi-clock-cdc-reset/bm-safety.json

Regression and replay cases4/5

content/audit/evidence/multi-clock-cdc-reset/bm-regression.json

包盘点

包哈希: sha256:b2de957278ff801a
文件数: 7
可执行文件: 0
复核结论: publishable
复核团队: IC Hub 审核团队
复核时间: 2026-06-11

已知限制与下一步

适用边界

审核结论只覆盖 Skill 包内容、安装计划和公开样例，不替代真实 FPGA 项目的上板测试、客户验收和安全审批。

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